A synchronous decoder for self-clocking signals.

摘要

The invention is a synchronous decoder for self-clocking signals which uses a single, high frequency reference clock signal. The incoming signal is sampled at a very high rate ; a shift register temporarily stores the incoming samples. A window pointer register selects a particular bit of the shift register as the output signal. The position of the window pointer is maintained by a feedback loop which tracks any phase error in the incoming signal and shifts the window pointer accordingly. As a result, the output signal remains in phase lock with the incoming signal.