| 摘要 |
A scrambling system produces two load signals during one horizontal period, and achieves the result that obtains three address transitions by two address transitions. The system comprises two line memories (2a,2b) for alternately storing the digital data of the composite video signal (Vin) according to the write address counter (4), an irregular address generater (21) for providing the irregular address to a read address counter (5), a horizontal feedback interval detector (22) for detecting the horizontal feedback interval including the front porch interval of the previous horizontal scanning line and the back porch interval of the present horizontal scanning line, a clear signal generater (23) for providing the clear signal to the write and read address counters (4,5), a load signal generater (24), a comparator (25) for comparing the output address of a read address counter (5) with the line rotation value, and an AND gate (AD1).
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