| 摘要 |
PURPOSE:To perform the limit operation in an arbitrary position by outputting a prescribed limit value at the time of the occurrence of overflow in an arithmetic unit for operation of data adopting complementary expression. CONSTITUTION:A limit discriminating circuit 104 discriminates whether n-th to 17th bits designated by a limit indicating signal LMT out of an operation result F(A, B) obtained by operation of data to be operated extended to 17 bits in an MSB adding circuit 101 have the same value or not, and this circuit 104 outputs a limit discrimination signal 113 in the high level when they have the same value. In this case, an inverter gate group 107 is turned off, and the operation result F(A, B) is not outputted to an output bus 112, and a limit value output circuit 105 is operated to output the upper or lower limit value of the number (n) of bits through an inverter group 108. Thus, not only the output value is so limited that it can be expressed by 16 bits but also the output value is so limited that it can be expressed by the arbitrary number (n) of bits. |
