发明名称 LOGICALLY VERIFYING DEVICE
摘要 PURPOSE:To improve the design quality, reduce the development cost, and shorten the design period by evaluating a real circuit with LSI design data. CONSTITUTION:The electric signal outputted by the real circuit 6 is inputted to an electric signal-input pattern converting means 3. The electric signal-input pattern converting means 3 sends a pattern to a simulator 2 by an input pattern input means 1. Then the specification of a signal to be generated is set for the simulator 2 by a signal specification setting means 5, the operation frequency of the simulator 2 is set by an operation frequency setting means 4, and simulation is performed. At this time, the fundamental clock and input pattern of the simulation are synchronized with the fundamental clock of the real circuit 6 through the electric signal-input pattern converting circuit 3 and then deviation in operation between the real circuit 6 and simulator 2 is eliminated. The simulation result which is thus obtained can be confirmed on a display 9.
申请公布号 JPH04283868(A) 申请公布日期 1992.10.08
申请号 JP19910048453 申请日期 1991.03.13
申请人 MITSUBISHI ELECTRIC CORP 发明人 SUDA SHINJI;HORI TOSHIHIKO;TANABE KYOKO
分类号 G01R31/28;G06F11/22;G06F11/25;G06F11/26;G06F17/50 主分类号 G01R31/28
代理机构 代理人
主权项
地址