| 摘要 |
PURPOSE:To attain a high speed access without increasing the chip area by improving the read-out column gate. CONSTITUTION:The read-out column gate 23 is constituted with nMOSes 24, 25 and the gates of these nMOSes 24, 25 are connected respectively to bit lines BL and BLX and the drains are connected respectively to data buses DB and DBX and the sources are connected to a read-out column selection line CLR on common, and the potential of the read-out column selection line CLR is set at Vcc [V] at a non selection time and at O [V] at a selection time. |
