发明名称 |
DCT MATRIX ARITHMETIC CIRCUIT |
摘要 |
<p>PURPOSE:To reduce the number of multipliers and adders and to reduce the gate scale of an arithmetic circuit. CONSTITUTION:A DTC converstion coefficient is stored in a coefficient ROM part 1 and a multiplication part 2 multiplies input data by the DCT conversion coefficient. An addition part 3 adds a multiplication result with a previous operation result selected in a selector 5 and a result is held in plural registers 4. At that time, a control part 6 selects the inputs of the plural registers 4 and selects the output of the selector 5. A processing for sequentially multiplying and adding to one piece of input data by the plural DCT conversion coefficients from the coefficient ROM part 1 and for sequentially updating the plural registers 4 by the operation result is executed for the number of elements times in the row-direction of a DCT matrix. The request of the row-direction of the ECT matrix is obtained and the operation is executed for the number of the elements times of the column-direction of the DCT matrix. Then, all the elements in the row-direcion and the column-direction of the DCT matrix are obtained.</p> |
申请公布号 |
JPH04280368(A) |
申请公布日期 |
1992.10.06 |
申请号 |
JP19910067703 |
申请日期 |
1991.03.08 |
申请人 |
FUJITSU LTD |
发明人 |
IWAMA MASAYASU;KAWAI OSAMU |
分类号 |
H04N1/41;G06F17/14;G06T1/20;H04N19/42;H04N19/423;H04N19/60;H04N19/625 |
主分类号 |
H04N1/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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