| 摘要 |
PURPOSE:To prevent logical malfunction due to the synchronization operation of an output circuit and to simplify the design by providing a through-rate control circuit slowing down the falling time of an output signal from the output circuit. CONSTITUTION:The output circuit outputting a high level or a low level output signal SOUT in response to an input signal SIN from an internal logic circuit is provided with a through-rate control circuit 30 including a MOS transistor(TR) 16, a NOR gate 17 and a selector circuit 18. The selector circuit 18 is set so that, when a through-rate control signal CIN is at a high level, the output signal SOUT is selected and when the through-rate control signal CIN is at a low level, the input signal from an inverter 1 is selected. Thus, when the through-rate control signal CIN is at a high level and when the output signal SOUT is going to down to a low level from a high level, a low level signal is inputted to a gate of the MOS TR 16 and the MOS TR 16 is turned off to slowdown the falling time of the output. |
