发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 <p>PURPOSE:To prevent the malfunction of a system that is caused by the delay time of a delay circuit for a clock generator using the delay circuit. CONSTITUTION:A timing generator 1-3 outputs a system clock with the output of an oscillation circuit 1-1 and the output of a delay circuit 1-2. The counters 1-4 and B 1-5 counts the outputs of the circuit 1-1 and the generator 1-3 respectively. The counter B 1-5 is controlled by the output of a counter A 1-4, and a reset circuit 1-6 resets the system with the output of the counter B 1-5.</p>
申请公布号 JPH04278614(A) 申请公布日期 1992.10.05
申请号 JP19910041449 申请日期 1991.03.07
申请人 NEC CORP 发明人 HARA ATSUHIRO;KAWADA KAZUHIDE
分类号 G06F1/06 主分类号 G06F1/06
代理机构 代理人
主权项
地址
您可能感兴趣的专利