发明名称 INTERFACE CIRCUIT AND PHASE LOCKED LOOP USED THEREFOR
摘要 PURPOSE:To improve the reliability of the circuit operation by making an oscillating frequency of a phase locked loop stable so as to give a reference clock not including jitter to each circuit section. CONSTITUTION:A voltage fluctuation of an output PD of a phase comparator 12 is unsharpened by decreasing a drive capability of an output section of the phase comparator 12 of a phase locked loop 10 generating a reference clock BCK after the reference clock BCK is synchronized with a transmission signal DIN from a sender side equipment and jitter included in the output PD is sufficiently absorbed by a low pass filter 13 thereby slowing down the fluctuation of the oscillating frequency of a voltage controlled oscillator 14 against a change in the output PD of the phase comparator 12.
申请公布号 JPH04271635(A) 申请公布日期 1992.09.28
申请号 JP19910032927 申请日期 1991.02.27
申请人 SANYO ELECTRIC CO LTD 发明人 KIYOSE MASASHI
分类号 H03L7/10;H04L7/033 主分类号 H03L7/10
代理机构 代理人
主权项
地址