PARALLELLSERIALLPARALLEL DATA CONVERTER

摘要

PURPOSE:To realize a highly efficient transmission/reception of data, by securing a synchronism through a simple constitution for each sampling signal during the parallel/serial and serial/parallel data conversions. CONSTITUTION:The D-FF15 divides the reference clock signal SCK1 into two parts to deliver the clock signal CK1 of 25Hz frequency through the output terminal Q. The D-FF45 divides the reference clock signal SCK2 into two parts to deliver the clock signal CK2 of 25Hz frequency through the output terminal Q'. The 1st and 2nd counters 16 and 46 count the pulse numbers of the signals SCK1 and SCK2 and then generate the sampling output signals for conversion of data while switching the output terminals successively according to the count number. The counter 46 starts counting by the start of counter 16 to give a compensation to the delay of operation for the counter 46 to the counter 16.