| 摘要 |
PURPOSE:To avoid an overflow in a fixed point arithmetic operation at high operation speed with a simple circuit construction by providing 1-bit head margin and shifting the decimal point when the overflow takes place. CONSTITUTION:N-bit addition data A is inputted to a computing element 14 and n-bit added data B is inputted to the computing element 14 through a multiplexer 16. The computing element 14, which serves to conduct the (n+1)-bit addition, conducts a calculation of (B+A), and the calculation result is inputted to a shifter 18. The overflow state of the calculation result is detected and inputted to a controller. When the overflow takes place in the process of an accumulated addition and subtraction, the decimal point is shifted, and when a state in which the decimal point may be restored to the original position is brought about, the decimal point is restored to the original position. |
