| 摘要 |
PURPOSE:To shorten the processing time of a processor by providing a second private bus to shorten the machine cycle. CONSTITUTION:Not only a data RAM 2 and a data ROM 3 connected to a data bus 1 are provided but also a multiplier block having a multiplier 8 as the center and a computing element block having a computing element as the center are provided. Further, a first private bus 10 through which the multiplication result of the multiplier 8 is transferred to an input register 12 of the computing element 14 before being latched in an output register 9 and a second private bus 16 through which the operation result of the computing element 14 is transferred an input register 5 through a multiplexer 4 for the multiplier 8 before being latched in an output register 15. |
