| 摘要 |
PURPOSE:To reduce a channel switching time without losing responsiveness and spriousness by selecting either mode of a high speed lockup and a steady- state operation of a PL with a simple means in the PLL frequency synthesizer controlling the frequency of a radio transmitter-receiver. CONSTITUTION:A reference frequency of a fixed oscillator 11 is divided by a frequency divider 12 whose frequency division number is variable, a variable frequency divider 18 provided to a feedback circuit in which an output frequency of a voltage controlled oscillator 15 is fed back to a phase comparator 13 is inserted between a couple of interlocking switches 16, 17 respectively selecting the high speed lockup operation and the steady-state operation at the input and the output side of the comparator, and a variable frequency divider 19, a 2-modulus pre-scaler 20 and pulse swallow counters 21, 22 are connected in cascade between high speed moving contacts of the said switches, and a control section 23 gives a command to each frequency divider, a loop filter 14, the switches and the counters. |
