| 摘要 |
PURPOSE:To prevent a through current from being generated in the case of an intermediate potential and to respond to a change at high speed even when the transition of an input signal is smooth by using a signal delaying an output. CONSTITUTION:Pch FET P11 and P12 and nch FET N11 and N12 have driving ability at the same degree, and the absolute value of a threshold voltage is lower than a middle point at the height of a power supply potential. These FET are connected between power sources as prescribed, and an input signal and a feedback signal are applied to a prescribed gate terminal. The signal delay time of a delay circuit 1 is set larger than the rise/fall time of the input signal. Therefore, the level of the output signal is held until the normal state of the FET is established by the transition of the input signal level, all the FET are simultaneously conducted, and the through current is prevented from being generated. The transistor size of an inverter 2 is made enough small in comparison with the P11-N12, and current driving ability is set low. When a logic circuit is turned to a normal state, the inverter 2 prevents the output terminal from turning to a floating state and establishes an output signal potential. |
