| 摘要 |
<p>PURPOSE:To prevent generation of an erroneous pulse to an output signal even when 1st and 2nd clock signals are selected at an optional time by correcting a phase difference between the 1st and 2nd input clock signals by a delay circuit and inputting the result to a changeover device. CONSTITUTION:A phase comparator 1 outputs a digital control variable corresponding to a phase difference between 1st and 2nd clock signals inputted to input terminals 10,20. A delay device 2 delays the 1st clock signal from the input terminal 10 by a prescribed time and outputs the delayed signal. A control delay device 3 delays the 2nd clock signal from the input terminal 20 by a delay time in response to the digital control variable from the phase comparator 1 and gives an output. A changeover device 4 outputs the 1st or 2nd clock signal delayed by a switching signal inputted from a terminal 30 to a terminal 40.</p> |
