| 摘要 |
PURPOSE:To prevent the gain from being decreased even when the phase difference of two inputted signals is nearly O by adding a prescribed pulse width to a pulse having a pulse width corresponding to the phase difference of the two signals. CONSTITUTION:A delay detection circuit 15 to detect the arrival of a delay signal between two signals fv, fr and a pulse addition circuit 16 adding a pulse having a prescribed pulse width to a phase difference signal outputted from a phase difference detector 10 when the delay detection circuit 15 detects a delay signal are provided between the phase detector 10 and an analog computing element 14. A delay signal ffv or ffr having a prescribed pulse width is added to phase difference signals Av, Ar and the resulting signals are inputted to the analog computing element 14. Thus, even when the phase difference between the input signals fv and fr is close to zero, the analog computing element 14 receives the delay signal ffv or ffr with a prescribed pulse width without fail. |
