| 摘要 |
PURPOSE:To make stable read and high-speed write possible, by controlling the memory cell holding current to a smaller value at the write time in comparison with that at the read time. CONSTITUTION:The holding current is supplied to the other emitters of transistors Q1 and Q2, which form the holding FF of memory cell C, from constant-current circuit IST' corresponding only to selected cell C and constant-current circuit IST, and the margin of the holding level to the reference voltage is enlarged to perform a stable read operation. At the write time, the switching circuit formed by differential transistors Q3 and Q4 of circuit IST' is cut off by write control signal anti-WE, and constant-current supply from circuit IST' is broken approximately synchronously with write voltage VWL. Then, base voltage VCOS of the low-level side transistor of the FF rises according to reduction of voltage drop of the load resistance corresponding to current drop. Consequently, the base voltage of the turn-off transistor rises, and the voltage difference between this voltage and voltage VWL which turns on this transistor is enlarged to perform a high-speed write operation. |
