| 摘要 |
A dual privilege level coprocessor which is especially suited for use in a software asset protection system is described. The coprocessor includes a supervisor processing element and an application processing element. The supervisor processing element includes a supervisor processor and dedicated supervisor random access and read only memory. The application processing element includes an application processor, an application random access memory, a secure random access memory, a low privilege read only memory, and a high privilege read only memory. An internal bus couples the supervisor processor, application processor, high and low privilege random access memories, application random access memory and secure random access memory. The high privilege read only memory and the secure random access memory are enabled only in response to dedicated control signals from the supervisor processor. While the application processor in combination with the low privilege random access memory has many general purpose computing capabilities, it is incapable of executing input or output operations. An input/output device is also coupled to the bus and controlled by the supervisor processor. The secure random access memory is provided for storage of sensitive information such as decryption keys. The coprocessor implements a low privilege level of operation for the purpose of executing protected software which is first decrypted under the control of the supervisor processor and then stored in the application processor random access memory. The coprocessor is also capable of high privilege operation either by the supervisor processor alone or with the supervisor processor controlling the application processor.
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