| 摘要 |
An output buffer circuit for outputting data from a memory device uses a driving means pumped under a specific value of power and a pulldown transistor driving means to improve the data output speed and remove the noise upon the output of data. The circuit comprises a latch (1) for receiving the data signals from data buses to output the state signals, NAND gates (ND1,ND2,DN3) for processing the state signals, NAND gates (ND1,ND2,ND3) for processing the state and data output signals, a control circuit (2) having MOS TR's (M3,M4,M5), pumping capacitors (C1,C2) and a pumping circuit (3) to process the output signals of the NAND gates (ND1,ND2), a "1" level control circuit (11) having a NOR gate (NOR1) and a pumping capacitor (C3), and a "0" level control circuit (12) having a NOR gate (NOR2) and MOS TR (M6).
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