| 摘要 |
A circuit for initialisation of the circuit verifying correctness of operation of real-time microprocessor control systems, especially in telecommunications characterized in that it contains a trigger (P1), the cascade of circuits containing AND gates (BI2,...,BIK-1) and triggers (P2,...,PK-1), instruction counter (LI) and AND gate (BIK), and the outputs of consecutive triggers (P1,...,PK-1) are connected to the inputs of gates of the further stage of the cascade (BI2,...,BIK), other inputs of such gates are connected to the outputs of the control system (SI2,...,SIK), outputs of gates (BI2,...,BIK-1) are connected to the setting inputs of triggers corresponding to them, output of overflow of instruction counter (LI) is connected to resetting inputs of all triggers, and the output of the trigger (P1) is additionally connected to the resetting input of instruction counter (LI).<IMAGE>
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