| 摘要 |
PURPOSE:To shorten the processing time by supposing carry and rounding to perform the operations in parallel processings in several divided blocks and outputting required one of operation results. CONSTITUTION:Data is divided to four blocks BLK0 to BLK3. The operation for carry from a lower block and rounding is performed in a first arithmetic circuit, namely, rounding circuits RND2 and RND3. The operation for no carry and rounding is performed in a second arithmetic circuit, namely, the rounding circuit RND2. The operation for carry and no rounding is performed in a third arithmetic circuit, namely, adders AAD2B and ADD3B. The operation for no carry and no rounding is performed in a fourth arithmetic circuit, namely, an adder ADD0 and ADD1A to ADD3A. First to fourth arithmetic circuits are executed in parallel to preliminarily obtain the operation results, and the final result is selected from them and is outputted in accordance with, the presence of carry and rounding process. |
