| 摘要 |
PURPOSE:To accelerate the phase following of a feedback signal to a reference signal by detecting a lagging error between the phases of first and second input signals by a third logic gate and a leading error by a fourth logic gate, respectively. CONSTITUTION:When an input signal R is changed to 1 first at a time t1, the output Q1 of an FFD 1 is changed to 1, and when an input signal V is changed to 1 at a time t2, the output Q2 of an FFD 2 is changed to 1. Therefore, both two input of an AND gate L1 are set at Hs, and output R1 goes to H, and the output Q1, Q2 of the FFDs 1, 2 are changed to 0s, and reset is cancelled again. Similarly, the output Q3, Q2, and Q4 go to Hs during time t3-4, t5-6, and t7-8, respectively, and the output Q1, Q3 are synthesized, and it goes to L during time t1-3, t3-4, and output D synthesizes the output Q2, Q4, and goes to L during time t5-6 and t7-8. Thereby, the phase error of the feedback signal for the reference signal R can be detected at the rise and fall of the Q1, Q3, which accelerates the phase following. |
