发明名称 METHOD AND APPARATUS FOR CONTROLLING DASD
摘要 PURPOSE: To optimize data transfer between a CPU with high performance and a DASD array, and the possibility of the usage of the DASD. CONSTITUTION: Access to logical tracks in KN pieces of blocks is managed by using K as the number of parity blocks. The KN pieces of blocks are dispersed to the arrays of N pieces of DASD having K pieces of blocks for one physical track of one DASD, and stored. The blocks are formatted to the array using the modulars of line measure order as a scale for balancing a data transfer ratio and concurrency (the number of the DASD connected by each access), and both the large amounts of access demands and the small amounts of access demands lined in random are executed for the array.
申请公布号 JPH04232557(A) 申请公布日期 1992.08.20
申请号 JP19910112196 申请日期 1991.04.18
申请人 INTERNATL BUSINESS MACH CORP <IBM> 发明人 JIEEMUSU TOOMASU BURADEI;RUUSU ENIDO SHINTORON;SUTEFUAN GOORUDOSUTEIN;JIIN HOOMINGU WANGU YUU;JIEISHIYANKAA MOOSEDASU MENON
分类号 G06F3/06;G06F11/10;G06F13/42;G11B20/10;G11B20/18 主分类号 G06F3/06
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