发明名称 PEAK HOLD CIRCUIT
摘要 PURPOSE:To prevent the effect of load variance, by controlling the charging via the emitter follower in synchronizing with the signal voltage according to the signal voltage and compared output with the capacitor photoelectric voltage for negative peak hold. CONSTITUTION:When a signal voltage is input to the line 11, the bias voltage is made to 0 V at the bias circuit 1, and the signal voltage is fed to the positive input terminal of the comparator 6 fed with the negative feedback voltage from the peak hold capacitor 13. Further, the signal voltage is great, the comparator 6 outputs a positive output, and as far as the gate circuit 2 is OFF in synchronizing with the signal voltage, the emitter follower is conductive, and the capacitor 5 is charged to the peak value of the signal voltage. Since the input current of the comparator 6 is generally small, the load variance can almost be neglected. Further, the input offset voltage is small, the output of the circuit 1 and the voltage on the charging line 13 of the capacitor 5 are substantially equal, allowing to prevent the production of noise and level shift due to load variance.
申请公布号 JPS56117395(A) 申请公布日期 1981.09.14
申请号 JP19800017772 申请日期 1980.02.18
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 FUJIKI MASAO
分类号 G11C27/00;G01R19/04;G11B21/10;G11C27/02 主分类号 G11C27/00
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