发明名称 METHOD AND APPARATUS FOR PARITY TEST FOR MEMORY CHIP
摘要 PURPOSE: To correct data or to stop the operation of a parity test device before the data are stored in a wrong memory by performing the parity check of the data and also address to detect an error in the early stage of a memory cycle. CONSTITUTION: The parity check function is carried out in a memory chip 10 by a 12-bit address parity check function circuit 40, a 9-bit data parity check function circuit 42 and a parity logical decoding circuit 44. The parity check function can be selectively carried out to be disabled and also can select the odd/even polarity to ensure the flexibility.
申请公布号 JPH04227549(A) 申请公布日期 1992.08.17
申请号 JP19910133729 申请日期 1991.03.29
申请人 NATL SEMICONDUCTOR CORP <NS> 发明人 DENISU ERU UENDERU;TERII RAIAN;ROBAATO PUROOBUSUTEINGU;CHIYAARUZU HOCHISUTEDORAA
分类号 G06F11/10;G06F12/16 主分类号 G06F11/10
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