| 摘要 |
The chip stabilized circuit for preventing the latch up generated by the parasitic bipolar structure in supplying the initial power source has a first clock dividing circuit (2) directly connecting to the pad (1), a second clock dividing circuit (3), a third clock dividing circuit (4) and inner direct current oscilation circuit (6). The chip stabilizer is operated by outer clock (CSIN) of the first clock dividing circuit. The inner direct current oscilation circuit and the first, the second clock dividing circuit (2,3) are operated by inner clock (CSOUT) of the chip stabilizer.
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