| 摘要 |
PURPOSE:To realize the large capacity of a stacked capacitor, to restrain the interference noise between individual interconnectios and to highly integrate a DRAM itself at the RAM of, e.g. an open-bit line structure. CONSTITUTION:Memory cells MC1 and MC2 which are constituted of switching elements and stacked capacitors C1 and C2 are formed in element formation regions 1 on a silicon substrate 15. Bit lines 2 which are connected electrically to the memory cells MC1 and MC2 are formed on the element formation regions 1 via an insulating layer 10. In addition, shielding electrodes 12 for bit-line shielding use are formed between the individual bit lines 2 via the insulating layer 10. A power supply (at a fixed potential) for bit-line shielding use is supplied to the shielding electrodes 12 from the rear of the silicon substrate 15. In order to constitute them, it is possible to use, e.g. a technique to paste silicon substrates used to form, e.g. an SOI (silicon on insulator) substrate and a selective polishing technique to a silicon substrate. |
