| 摘要 |
PURPOSE:To speed up the lock, by digitally discriminating the phase between a composite synchronizibg signal and a horizontal synchronizing signal obtained through the separation of an input video signal and stopping an input clock pulse. CONSTITUTION:A composite synchronizing signal (a) can be obtained from an amplifying circuit 6 and a synchronizing separation circuit 7 from a video signal V. Further, PLL consists of a horizontal synchronizing phase detector circuit 2, low pass filter 3, voltage controlled oscillator 4, AND gate 8 and horizontal pulse counter 5. Further, when the phase between the composite synchronizing signal (a) and the horizontal synchronizing signal (b) is not matched, the output signal (c) of the analog switch 9 is at low level and the AND gate 8 is locked, allowing to lock the clock pulse (d) and to give a delay for the output of the horizontal pulse counter 5. Further, when the phase between the signals (a) and (b) is agreement, the output signal (c) is at high level and the AND gate is open, allowing AFC operation by PLL. |
