| 摘要 |
PURPOSE:To prevent the measured error, by providing a frequency synthesizing means to set always the intermediate frequency signal, which is obtained from the modulation signal and the demodulation signal, to a single frequency. CONSTITUTION:Under the state where PLL circuit 20 is locked, mixer 21 outputs the signal of the difference between the modulation signal and the local frequency signal, which is the output of voltage control oscillator 24, to phase difference detector 22. Phase difference detector 22 detects the phase difference between this difference signal and the first intermediate frequency signal. Under the state where PLL circuit 20 is locked, frequencies and phases of these two signals are synchronized with each other, and the first intermediate frequency signal and the second intermediate frequency signal become always equal. |
