| 摘要 |
A method for checking parity on, for example, an Extended Industry Standard Architecture (EISA) bus. In a 32-bit information bus, four parity pins may be provided. During a first clock cycle the pins are all driven high and during a second clock cycle the pins are all driven low. This characteristic pattern is detected by a slave device and provides an indication that parity data will be transmitted on the four parity pins. After an indication of parity support the pins are provided with parity bits for error detection. |
