发明名称 |
SEMICONDUCTOR INTEGRATED CIRCUIT |
摘要 |
<p>PURPOSE:To speed up reading out by transmitting the information of memory cells to be selected of memory array to common data lines via one of plural sub-common data lines and sense amplifiers corresponding thereto. CONSTITUTION:The common data line pairs CDL1 to 4 of the memory array M-ARY 1 to 4 consisting of CMOSs are constituted of respectively 4 sets of the sub-common data line pairs. The sense amplifiers SA 1 to SA 4... consisting of bipolar transistors are connected to each of the sub-common data pairs. the information from the memory cell among the memory arrays M-ARYs 1 to 4 selected via MISFETs for switching are selected via the sense amplifier connected to the sub-common data lines in the reading out operation. The floating capacity of the sense amplifier input terminals is decreased in this way and the high-speed reading out is possible.</p> |
申请公布号 |
JPH04212789(A) |
申请公布日期 |
1992.08.04 |
申请号 |
JP19910019982 |
申请日期 |
1991.02.13 |
申请人 |
HITACHI LTD |
发明人 |
OGIUE KATSUMI;SUZUKI YUKIRO;MASUDA IKUO;ODAKA MASANORI;UCHIDA HIDEAKI |
分类号 |
G11C11/41;G11C11/414;G11C11/417;H03K19/0175;H03K19/08 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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