MOSFET with very short channel lengths - uses a multiple implant of dopant in source-drain regions to provide an abrupt, shallow box-shaped dopant profile to minimise punch through

摘要

The MOS transistor, consisting of drain/source regions (5) and a gate electrode (3) on top of the gate insulator (2), which defines a channel, also has a polycrystalline Si (polySi) layer (6) on the diffused regions. The dopant, pref. P or As, profile featured pref. has a peak value around 10 power (20) cm-3 at the surface, and a min. depth, pref. about 0.15 micron at which the concn. is about 10 power (19) which is greater than the channel current depth below the surface, after which the concn. rapidly decreases. The gate electrode pref. has an insulation film (4) on sides and top and the polysilicon layer extends onto the insulation layer. After formation of the field-oxide (8) and gate electrode structure (2,3,4) a polySi layer (6) is deposited on the diffusion regions and defined. Then multiple implantations are carried out to build the desired impurity profile. Also claimed is a process in which a first implant is made before the polySi layer (6) has been deposited and after the gate electrode and its insulations have been defined. The first implant is pref. As at 350 KeV with a dose of about 5x10 power (14) cm-2, a second implant, made after deposition and defining the polySi layer, is pref. 10 power (16) cm-2 at 60 KeV. Also claimed is the possible use of a third implant. The dopant is activated by a heat treatment. USE/ADVANTAGE - The profile is intended to approximate that of a constant dopant concn. over a min. depth of about 150nm, and then a sharp decrease of the dopant concn.. This avoids the punchthrough effect between source and drain during operation of the transistor and prevents the diffusion area conductivity being influenced by the gate bias. The profile allows transistors to be made in submicron channel lengths, e.g. down to less than 0.5 micron.