| 摘要 |
<p>PURPOSE:To simplify an analog circuit by converting plural analog input signals to digital data in a time division with an A/D converter, processing this digital data converted in a time division with a logic circuit and obtaining the data in a desired timing. CONSTITUTION:In the case of deriving the data in a necessary timing, for instance, the timing of An from the data An-1, Bn-1, Cn-1, An, Bn, Cn... subjected to A/D conversion by different timings, An is used as data DA as it is, (Bn-1+2Bn) obtained by adding Bn-1 preceding by two of An and 2Bn doubling Bn succeeding by one of An is used as data DB, and (2Cn-1+Cn) obtained by adding 2Cn-1 doubling Cn-1 preceding by one of An and Cn succeeding by two of An is used as data DC. In such a manner, data in a necessary timing can be derived by interpolation from the data subjected to A/D conversion by different timings. Thus, by executing the interpolating executed by a logic circuit instead of a sample-holding circuit, an analog circuit is simplified, and S/N is improved.</p> |
