发明名称 DATA DELAY CIRCUIT
摘要 PURPOSE:To obtain an inexpensive circuit having a large delay amount by storing input data in the address wherein a memory in the specified delay amount is subjected to increment successively, and outputting them from the last address as the final delay data. CONSTITUTION:The input data are applied to an I/O terminal of the memory 10 through a buffer 12. The address is applied to a terminal A of the memory 10 from an address counter 11. In accordance with this address, a reading and writing at the same address are alternately repeated by the memory 10. The data read out from the memory 10 by the address of even and odd numbers are held by registers 13, 15 respectively. The data held by the registers 13, 15 are applied to the I/O terminal of memory 10 through the buffers 14, 16 respectively. The final delay data read out from the memory 10 are held by a register 17 and outputted through a register 18. Thus, the circuit having the large delay amount can be constituted with the use of inexpensive memory.
申请公布号 JPH04205795(A) 申请公布日期 1992.07.27
申请号 JP19900332861 申请日期 1990.11.29
申请人 YOKOGAWA ELECTRIC CORP 发明人 KAWABUCHI ETSURO
分类号 G11C19/00;G06F5/06;H03H17/08 主分类号 G11C19/00
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