发明名称 POWER INVERTER SNUBBER CIRCUIT
摘要 A snubber circuit for a neutral clamped power inverter. The power inverter includes power transistors, a current sensor at the inverter output and a neutral clamping circuit connected between the inverter output and a neutral point in a DC power source which supplies the inverter. A controller circuit is connected to the current sensor, to the power transistors and to the neutral clamping circuit to selectively enable and disable the power transistors and the neutral clamping circuit in accordance with the inverter operation and current direction at the inverter output to minimize current transients at a load. An active snubber arrangement is provided to minimize snubber losses when the power transistors are inactive during alternate positive and negative half-cycles of operation.
申请公布号 US5130917(A) 申请公布日期 1992.07.14
申请号 US19910706452 申请日期 1991.05.28
申请人 ALLIED-SIGNAL INC. 发明人 SHEKHAWAT, SAMPAT S.
分类号 H02M7/48;H02M7/487;H03K17/0814 主分类号 H02M7/48
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