发明名称 DYNAMIC TYPE SEMICONDUCTOR MEMORY
摘要 PURPOSE:To enable high-speed sensing stable and with a reduction in power consumption by dividing a bit line into two groups, one for a Vcc precharging and the other for a Vss precharging. CONSTITUTION:A bit line couple divided into two groups is precharged at an earth potential Vss in a first group and at a power source potential Vcc in the second group. Now, as charge transfer means at an initial sensing, a transfer gate Q45 is provided between a common source node linked to a transistor for activation of a bit line sense amplifier 31 in the first group and a common source node linked to a transistor for activation of the bit line sense amplifier 32 in the second group. Then, when the transfer gate Q45 is turned ON at the initial sensing time immediately before the activation of the sense amplifiers, a shortcircuiting is caused between a 'L' level output side bit line-BLh in the second group and a 'H' level output side bit line BLe in the second group through the transfer gate Q45. This enables a high-speed sensing operation stable even under a low power source potential.
申请公布号 JPH04184787(A) 申请公布日期 1992.07.01
申请号 JP19900314764 申请日期 1990.11.20
申请人 TOSHIBA CORP 发明人 WATANABE YOJI
分类号 G11C11/409;G11C11/401;G11C11/41;H01L21/8242;H01L27/108 主分类号 G11C11/409
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