发明名称 FAULT DETECTING CIRCUIT
摘要 PURPOSE:To decrease the capacity of a pass indicator by indicating only an error display register(EIF) and effective bits of the EIF which are set at the same time by a pass indicator. CONSTITUTION:This circuit is provided with a PASS flip-flop 80 which sets only SL flip-flops 50 and 60 corresponding to registers 10 and 20 while an error display register(EIF) flip-flop 70 is set. Therefore, the select conditions of, for example, the register 10 where an error occurs are set in the pass indicator 80 simultaneously with the setting of the EIF 70 and the select conditions of the register 10 where the error occurs are left. Thus, the select conditions corresponding to all the registers are not set in the pass indicator, so the hardware quantity is reducible.
申请公布号 JPH04181333(A) 申请公布日期 1992.06.29
申请号 JP19900309642 申请日期 1990.11.15
申请人 NEC IBARAKI LTD 发明人 TSUKAHARA KATSUMI
分类号 G06F11/22 主分类号 G06F11/22
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