ERROR CORRECTING ENCODER/DECODER FOR A DIGITAL TRANSMISSION INSTALLATION

摘要

An encoder and decoder for use with a Wyner-Ash code whose memory order m is not less than six. Both the encoder and decoder operate in series by means of six shift registers connected in series, thereby making it possible to calculate a check bit on encoding in parallel by means of respective exclusive OR circuits, and consequently also making it possible to calculate a syndrome bit on decoding by a complementary exclusive OR circuit. Successive syndrome bits specify the position of an error in a received message, and the error is then corrected in the last shift register of the decoder.