发明名称 UNLOCK STATE DETECTING CIRCUIT FOR PLL CIRCUIT
摘要 PURPOSE:To detect a lock state surely in a weak modulation video input by receiving a beat signal generated in the output of a phase comparing circuit in the unlock state of a phase locked loop feed back circuit (PLL circuit) with an alternating current connection. CONSTITUTION:The output of a current output type phase comparing circuit 33 is connected to a resistance element R2 and the input of a beat signal amplifier circuit 37. When a PLL circuit 35 is in the unlock state, the waveform of the beat signal of the signal of a terminal 1 and a terminal 4 is generated, and this signal is amplified in the beat signal amplifier circuit 37 and transmitted to a flow rectifying circuit 38. The signal rectified in the flow rectifying circuit 38 is smoothed in a smoothing circuit 39, and the level of an output voltage waveform in proportion to the size of the inputted signal is obtained. And this voltage and the level of the output voltage waveform of a reference voltage circuit 41 are inputted in a voltage comparing circuit 40, and compared with reference voltage, then the PLL circuit 35 is discriminated as the unlock state, and the flow frequency band of a filter circuit 34 is extended. Thus, it is possible to detect the unlock state accurately.
申请公布号 JPH04172089(A) 申请公布日期 1992.06.19
申请号 JP19900300116 申请日期 1990.11.06
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 NIIMURA TETSUYA
分类号 H04N5/455;H03L7/095 主分类号 H04N5/455
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