| 摘要 |
PURPOSE:To enable the title circuit to have a large number of variable stages, to make the delay adjusting width narrower, and to make adjustment while allowing the device to operate by constituting an input-output circuit by connecting a large number of circuits which select two buses having delay differences in multiple stages. CONSTITUTION:The delays between each paired buses 3 and 4, 5 and 6, 7 and 8, and 9 and 10 are respectively set at (a), (b), (c), and (d) and a relation a<b<c<d is set among the delays. In addition, by switching the input setting of two external input terminals 11 and 12 for selecting delay, the outputs of gates 13 and 14 for selecting buses are switched to each other and the time until a input signal from an input terminal 2 is outputted from an output terminal 2 can be changed among (a+c+z), (a+d+z), (b+c+z), and (b+d+z). The (z) represents the sum of the delays by means of an input bus, output bus, and gate. Therefore, the delays can be adjusted while a device is operated. |
