| 摘要 |
of the Invention A synchronous changeover device detects both peak amplitude and pulse width, automatically switching between sets of signals when a fault is detected without a noticeable glitch. The signals of each set are peak detected and combined so that if any signal of a set falls below a predetermined value a FAIL signal is output to a switch timing and control circuit. The FAIL signal, together with the sync signals from the sets of signals, causes an electronic switch to switch from one set of inputs to another between sync pulses, resulting in a synchronous changeover. Further the signals are input to a start/stop counter via a multiplexer under control of a microprocessor. The counter counts the number of pulses of a reference signal between the start and stop of a selected signal pulse, and the microprocessor determines if the pulse width is within acceptable limits. Out of limits pulse widths cause the microprocessor also to generate the FAIL signal to automatically switch between sets of signals. |
