发明名称 DUPLEXING PHASE SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To eliminate the need for a large phase margin by connecting a timing extraction circuit to the output terminal of a selector so as to avoid rapid fluctuation in the phase of an output clock signal. CONSTITUTION:A timing extraction circuit 10 connected to the output terminal of a selector 9 consists of a narrow band pass filter whose center frequency is, e.g. set to the frequency of a clock signal. Then even when the input phase of the clock signal is changed by 180 deg. stepwise at a point B, the output phase is changed continuously by 180 deg.. Suppose that the clocks 1, 2 have the phase difference of 180 deg. being the worst phase difference, when a control signal is inputted to a selector control input terminal 102 at a point B, the selector output acts on selecting the clock 2 from the clock 1 and the clock signal having the phase discontinuity of 180 deg. at the point B. However, the timing extraction circuit 10 sends an output clock signal whose phase is continuously fluctuated from the point B according to the input output characteristic to an output terminal 103. Thus, no large phase margin is required and the malfunction at the switching is reduced.
申请公布号 JPH04162826(A) 申请公布日期 1992.06.08
申请号 JP19900289743 申请日期 1990.10.25
申请人 NEC CORP;NEC SHIZUOKA LTD 发明人 MAKISHITA YUUJI;YOSHIYAMA MASAAKI
分类号 H03L7/08;H03L7/087 主分类号 H03L7/08
代理机构 代理人
主权项
地址