| 摘要 |
The ROM data comprator adopts sequential logic circuit including DE flip-flop and peripheral transistor-transistor logic to compare the ROM data in high speed. The output pairs (Q2,Q6), (Q3,Q5), (Q3,Q4) are connected to an address generator (IC2), input terminals (OE,CE) of ROMs (IC4,IC5) and a logic circuit (IC6) respectively. Input terminals of demultiplexer (IC9) for selecting AND gate (I1-I4) according to input signal of switches (S1,S2) is connected to a DE-flip-flop (IC1) and DE flip-flop (IC7) and output terminal is connected to a power terminal (Vcc). A switch (S3) for supplying reset and set signal is connected to AND gates (I5,I9), NAND gate (N1), clear terminal of DE flip-flops (IC7,IC10), and input terminal of the logic circuit (IC6). The output terminal (QA-QH), (D0-D7) are connected to the ROM (IC4) and the AND gate (I9).
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