| 摘要 |
This invention concerns the technical field of digital telecommunications. In particular the invention concerns synchronous and plesiochronous digital hierarchical systems and a method and device for transferring information between such systems. The device according to the invention consists of an asynchronous buffer which separates the SDH system from the PDH system. The data signal entering the buffer DATAin can contain a so-called bit adjustment. In bit adjustment the incoming data signal is contained in a frame with one bit more than nominal or one bit less than nominal. The rate of writing into the buffer varies depending upon whether bit adjustment takes place or not. In order to regulate the rate of reading from the buffer so that it follows the rate of writing, the device comprises a FIFO register in which writing and reading of the data information takes place. For writing write addresses WADR are generated and for reading read addresses RADR are generated. The device comprises an average value calculator 38 which generates average value addresses AVADR around which the write addresses WADR oscillate. If the write addresses WADR as a result of the bit adjustment deviate too much from the average value addresses AVADR then the generation of average value addresses AVADR is hastened or delayed in stages so that the write addresses again oscillate within permitted limits around the average value addresses. The generated average value addresses are used in order to adjust the reading rate. If the read address deviates too much from the average value address then the reading speed out of the buffer is too high, whereupon the reading is stopped temporarily so that the rate of reading becomes the same as the rate of writing. The device comprises a first phase detector 33 for controlling the average value calculator 38 and a second phase detector 40 for regulating the speed of reading from the FIFO register. <IMAGE> |
