发明名称 SIMULATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To decrease the number of gates of a timing check circuit by adding the logic data of a timing detecting circuit part except a decision circuit part to a sequence circuit, outputting the detection signal of the detecting circuit part to an external device, and deciding whether or not a normal simulation signal is inputted or not by the external device according to a decision program. CONSTITUTION:Each simulation signal inputted to the sequence circuit is detected by the timing detecting circuit part 3 and the detection signal generated by the timing detecting circuit part 3 is inputted to the external device 13 which has the decision program for deciding the detection signal. The external device 13 decides whether or not the inputted simulation signal is normal with the detection signal according to the decision program. Consequently, the decision circuit part is replaced with the decision program provided to the external device 13, so the number of the gates can be decreased correspondingly.
申请公布号 JPH04153882(A) 申请公布日期 1992.05.27
申请号 JP19900279823 申请日期 1990.10.18
申请人 FUJITSU LTD;FUJITSU VLSI LTD 发明人 HIRATA YUKIO
分类号 G06F11/22;G06F11/25;G06F11/26;G06F17/50 主分类号 G06F11/22
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