| 摘要 |
PURPOSE:To reduce the operation time of the processor by providing a means which generates and outputs an interrupt signal only when operation data are extended to extension bits in an accumulator. CONSTITUTION:In response to the input of data 101, the contents of the data of an accumulator 2 and register 3 or memory 4 are operated by means of an arithmetic and logic unit 1 and the operated results of the unit 1 are inputted to the accumulator 2. The content of the data of the accumulator 2 is transferred to the register 3 or memory 4. At the moment the content is transferred to the memory 4, data 103 containing the value of a code sent from the accumulator 2 and the value of extension bits are decoded by means of an interruption generation circuit 5 and, when the data 103 are extended to extension bits, an interrupt signal 104 is outputted. Therefore, the number of judging steps can be reduced from the flowchart related to the presence/absence of an overflow and the arithmetic processing time of this fixed-point processor can be reduced. |
