发明名称 |
BIT SYNCHRONIZER |
摘要 |
A paging receiver capable of bit synchronizing to one of two data rates. The receiver has a digital phase locked loop integrated onto a single integrated circuit clocked by a single frequency crystal. The paging receiver receives and synchronizes to a POCSAG signal which may be transmitted at either 512 bits per second or 1200 bits per second. The digital phase locked loop bit synchronizes to either data rate using a single crystal frequency of 76.8 kHz. The data rate is selected by a bit in the code paging receiver's code plug. The digital phase locked loop is constructed to have a substantially constant frequency to bandwidth ratio at both data rates.
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申请公布号 |
US5111486(A) |
申请公布日期 |
1992.05.05 |
申请号 |
US19890324277 |
申请日期 |
1989.03.15 |
申请人 |
MOTOROLA, INC. |
发明人 |
OLIBONI, MARK L.;WOLTZ, STEPHEN H.;DRAPAC, GEORGE A.;DAVIS, WALTER L. |
分类号 |
H03L7/06;H03L7/099;H04L7/033;H04L7/04;H04L7/10;H04W88/02 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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