| 摘要 |
<p>PURPOSE:To shorten the time spent in verification by providing a back gate applying circuit and applying a back gate to a memory cell except at the time of erasing and erase verification. CONSTITUTION:At the time of write before erasing, the back gate is applied to a p-type well 29 by a back gate applying circuit 30 to write '0' in all memory cells by the avalanche breakdown. When an erase pulse is applied to sources of memory cells after the end of write before erasing, the back gate applying circuit 30 is made inactive by a signal from an erasing/erase verifying control circuit 32. That is, application of the back gate to the p-type well 29 of the memory array part is stopped to set the earth level. Erasing is verified after the erase pulse is applied to a memory array 1. Thus, the verification time is shortened.</p> |
