EEPROM with memory cells contg. MOS with charge layer and control gate - has transistor with drain breakdown voltage adjuster for specified operational range

摘要

The FET comprises a semiconductor substrate (10), a source (24) and a drain (22) spaced from each other to define in the substrate a channel region, over which an insulated conductive layer (16), at least partially, extends in a capacitive coupling with the substrate. Over the layer an insulated control gate (20) is deposited. The FET contains additionally a device for adjusting the breakdown voltage of the drain such that it lies in the region between a first voltage capable to be applied to the drain during read-out, and a second voltage applied for discharge of the conductive layer. Pref. the drain is doped with impurity of specified density. ADVANTAGE - Large memory capacity and improved operational reliability.