DATA DEMODULATION CIRCUIT

摘要

PURPOSE:To constitute a synchronous detection circuit in digital so as to facilitate circuit integration by discriminating number of synchronizing signals included in a prescribed period of a clock obtained from a phase locked loop means and controlling the phase locked loop means depending on the result of discrimination. CONSTITUTION:A resulting signal of detecting a synchronizing signal outputted from a synchronizing signal pulse generating circuit 24 of a synchronizing signal detection circuit 2 and a signal resulting from frequency-dividing a clock extracted by a PLL circuit 3 at a frequency divider 34 are fed to a synchronizing signal number discrimination circuit 7. Then the synchronizing signal number discrimination circuit 7 counts number of synchronizing signal pulses generated for one period of a 2XFS clock signal and discriminates the count to be '0', '1' or '2' or over. The result of discrimination is fed to a phase comparator control circuit 8. The phase comparator control circuit 8 controls a phase comparator 31 based on the result of discrimination of number of synchronizing signals and PLL lock detection from a PLL lock detection circuit 6 to control indirectly the oscillating frequency from a VCO 33.